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SECTION: Special Section on Machine Learning for VLSI Physical Design
IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages
Article No.: 49, pp 1–23

The detail routing process is by far the most time consuming during the physical design flow. Routing starts with an estimation of timing slacks and aims to meet the timing specifications at signoff. In this paper, we propose an improved method to predict ...

Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking
Article No.: 50, pp 1–19

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. In this article, we propose two routability optimization ...

Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks
Article No.: 51, pp 1–19

A multiterminal obstacle-avoiding pathfinding approach is proposed. The approach is inspired by deep image learning. The key idea is based on training a conditional generative adversarial network (cGAN) to interpret a pathfinding task as a graphical ...

Open Access
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs
Article No.: 52, pp 1–31

The objective of a leakage recovery step is to make use of positive slack and reduce power by performing appropriate standard-cell swaps such as threshold-voltage (Vth) or channel-length reassignments. The resulting engineering change order netlist needs ...

Routability-driven Power/Ground Network Optimization Based on Machine Learning
Article No.: 53, pp 1–27

The dynamic IR drop of a power/ground (PG) network is a critical problem in modern circuit designs. Excessive IR drop slows down circuit performance and causes potential functional failures. Most industrial practices tend to over-design the PG network for ...

Worst-case Power Integrity Prediction Using Convolutional Neural Network
Article No.: 54, pp 1–19

Power integrity analysis is an essential step in power distribution network (PDN) sign-off to ensure the performance and reliability of chips. However, with the growing PDN size and increasing scenarios to be validated, it becomes very time- and resource-...

Open Access
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation
Article No.: 55, pp 1–22

Modern electronic design automation flows depend on both implementation and signoff tools to perform timing-constrained power optimization through Engineering Change Orders (ECOs), which involve gate sizing and threshold-voltage (Vth)-assignment of ...

Open Access
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction
Article No.: 56, pp 1–22

Accurate capacitance extraction is becoming more important for designing integrated circuits under advanced process technology. The pattern matching-based full-chip extraction methodology delivers fast computational speed but suffers from large error and ...

A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis
Article No.: 57, pp 1–20

The electromigration-induced reliability issues (EM) in very large scale integration (VLSI) circuits have attracted continuous attention due to technology scaling. Traditional EM methods lead to inaccurate results incompatible with the advanced technology ...

CmpCNN: CMP Modeling with Transfer Learning CNN Architecture
Article No.: 58, pp 1–18

Performing chemical mechanical polishing (CMP) modeling for physical verification on an integrated circuit (IC) chip is vital to minimize its manufacturing yield loss. Traditional CMP models calculate post-CMP topography height of the IC’s layout based on ...

A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions
Article No.: 59, pp 1–18

With the exceeding advancement in technology, the sophistication of attacks is considerably increasing. Standard security methods fall short of achieving the security essentials of IoT against physical attacks due to the nature of IoTs being resource-...

SECTION: Regular Papers
Open Access
SwitchX: Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars
Article No.: 60, pp 1–21

Memristive crossbars can efficiently implement Binarized Neural Networks (BNNs) wherein the weights are stored in high-resistance states (HRS) and low-resistance states (LRS) of the synapses. We propose SwitchX mapping of BNN weights onto ReRAM crossbars ...

SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference
Article No.: 61, pp 1–28

Privacy-preserving neural inference helps protect both the user input data and the model weights from being leaked to others during the inference of a deep learning model. To achieve data protection, the inference is often performed within a secure domain,...

Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation
Article No.: 62, pp 1–26

A growing number of embedded instruments is being integrated into System-on-Chips for testing, monitoring, and several other purposes. To standardize their access protocols, the IEEE 1687 (IJTAG) standard has defined a flexible network infrastructure. ...

A Chisel Framework for Flexible Design Space Exploration through a Functional Approach
Article No.: 63, pp 1–31

As the need for efficient digital circuits is ever growing in the industry, the design of such systems remains daunting, requiring both expertise and time. In an attempt to close the gap between software development and hardware design, powerful features ...



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