ACM Transactions on Design Automation of Electronic Systems

The detail routing process is by far the most time consuming during the physical design flow. Routing starts with an estimation of timing slacks and aims to meet the timing specifications at signoff. In this paper, we propose an improved method to predict ...

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. In this article, we propose two routability optimization ...

A multiterminal obstacle-avoiding pathfinding approach is proposed. The approach is inspired by deep image learning. The key idea is based on training a conditional generative adversarial network (cGAN) to interpret a pathfinding task as a graphical ...

The objective of a leakage recovery step is to make use of positive slack and reduce power by performing appropriate standard-cell swaps such as threshold-voltage (V_th) or channel-length reassignments. The resulting engineering change order netlist needs ...

The dynamic IR drop of a power/ground (PG) network is a critical problem in modern circuit designs. Excessive IR drop slows down circuit performance and causes potential functional failures. Most industrial practices tend to over-design the PG network for ...

Power integrity analysis is an essential step in power distribution network (PDN) sign-off to ensure the performance and reliability of chips. However, with the growing PDN size and increasing scenarios to be validated, it becomes very time- and resource-...

Modern electronic design automation flows depend on both implementation and signoff tools to perform timing-constrained power optimization through Engineering Change Orders (ECOs), which involve gate sizing and threshold-voltage (V_th)-assignment of ...

Accurate capacitance extraction is becoming more important for designing integrated circuits under advanced process technology. The pattern matching-based full-chip extraction methodology delivers fast computational speed but suffers from large error and ...

The electromigration-induced reliability issues (EM) in very large scale integration (VLSI) circuits have attracted continuous attention due to technology scaling. Traditional EM methods lead to inaccurate results incompatible with the advanced technology ...

Performing chemical mechanical polishing (CMP) modeling for physical verification on an integrated circuit (IC) chip is vital to minimize its manufacturing yield loss. Traditional CMP models calculate post-CMP topography height of the IC’s layout based on ...

With the exceeding advancement in technology, the sophistication of attacks is considerably increasing. Standard security methods fall short of achieving the security essentials of IoT against physical attacks due to the nature of IoTs being resource-...

Memristive crossbars can efficiently implement Binarized Neural Networks (BNNs) wherein the weights are stored in high-resistance states (HRS) and low-resistance states (LRS) of the synapses. We propose SwitchX mapping of BNN weights onto ReRAM crossbars ...

Privacy-preserving neural inference helps protect both the user input data and the model weights from being leaked to others during the inference of a deep learning model. To achieve data protection, the inference is often performed within a secure domain,...

A growing number of embedded instruments is being integrated into System-on-Chips for testing, monitoring, and several other purposes. To standardize their access protocols, the IEEE 1687 (IJTAG) standard has defined a flexible network infrastructure. ...

As the need for efficient digital circuits is ever growing in the industry, the design of such systems remains daunting, requiring both expertise and time. In an attempt to close the gap between software development and hardware design, powerful features ...