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NVSim-CAM: A circuit-level simulator for emerging nonvolatile memory based Content-Addressable Memory

Published:07 November 2016Publication History


Ternary Content-Addressable Memory (TCAM) is widely used in networking routers, fully associative caches, search engines, etc. While the conventional SRAM-based TCAM suffers from the poor scalability, the emerging nonvolatile memories (NVM, i.e., MRAM, PCM, and ReRAM) bring evolution for the TCAM design. It effectively reduces the cell size, and makes significant energy reduction and scalability improvement. New applications such as associative processors/accelerators are facilitated by the emergence of the nonvolatile TCAM (nvTCAM). However, nvTCAM design is challenging. In addition to the emerging device's uncertainty, the nvTCAM cell structure is so diverse that it results in a design space too large to explore manually. To tackle these challenges, we propose a circuit-level model and develop a simulation tool, NVSim-CAM, which helps researchers to make early design decisions, and to evaluate device/circuit innovations. The tool is validated by HSPICE simulations and data from fabricated chips. We also present a case study to illustrate how NVSim-CAM benefits the nvTCAM design. In the case study, we propose a novel 3D vertical ReRAM based TCAM cell, the 3DvTCAM. We project the advantages/disadvantages and explore the design space for the proposed cell with NVSim-CAM.


  1. [1].Predictive Technology Model. http://ptm.asu.edu/.Google ScholarGoogle Scholar
  2. [2].Agrawal B. and Sherwood T.. Ternary CAM power and delay model: extensions and uses. TVLSI, 16 (5):554564, may 2008.Google ScholarGoogle Scholar
  3. [3].Baek I. G. et al. Realization of vertical resistive memory (VRRAM) using cost effective 3D process. In IEDM, pages, dec 2011.Google ScholarGoogle Scholar
  4. [4].Bayram I. and Chen Y.. NV-TCAM: Alternative interests and practices in NVM designs. In NVMSA, pages 16, aug 2014.Google ScholarGoogle Scholar
  5. [5].Cha Nanoscale E. et al. (10nm) 3D vertical ReRAM and NbO2 threshold selector with TiN electrode. In IEDM, pages, dec 2013.Google ScholarGoogle Scholar
  6. [6].Chang M.-F. F. et al. A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-Ins search time. J SSC, 58: 318319, feb 2015.Google ScholarGoogle Scholar
  7. [7].Chi P. et al. PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In ISCA. volume 43, 2016.Google ScholarGoogle Scholar
  8. [8].Huang Chung-Hsun et al. Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. JSSC, 37 (1):6376, 2002.Google ScholarGoogle Scholar
  9. [9].Guo Q. et al. AC-DIMM: associative computing with STT-MRAM. In ISCA, pages 189200, 2013.Google ScholarGoogle Scholar
  10. [10].Huang L.-Y. et al. ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing. In VLSIC, pages 12, jun 2014.Google ScholarGoogle Scholar
  11. [11].Imani M. et al. ACAM: Approximate computing based on adaptive associative memory with online learning. In ISLPED, 2016.Google ScholarGoogle Scholar
  12. [12].Imani M. et al. Approximate computing using multiple-access single-charge associative memory. TETC, PP(99):11, 2016.Google ScholarGoogle Scholar
  13. [13].Imani M. et al. Processing Acceleration with Resistive Memory-based Computation. In Memsys, 2016.Google ScholarGoogle Scholar
  14. [14].Imani M. et al. ReMAM: low energy resistive multi-stage associative memory for energy efficient computing. In ISQED, pages 101106, 2016.Google ScholarGoogle Scholar
  15. [15].Imani M. et al. Resistive configurable associative memory for approximate computing. In DATE, pages 13271332, 2016.Google ScholarGoogle Scholar
  16. [16].Li J. et al. 1 Mb 0.41 um2 2T-2R cell nonvolatile team with two-bit encoding and clocked self-referenced sensing. JSSC, 49 (4):896907. apr 2014.Google ScholarGoogle Scholar
  17. [17].Li S. et al. Leveraging nonvolatility for architecture design with emerging NVM. In NVMSA, pages 15, 2015.Google ScholarGoogle Scholar
  18. [18].Li S. et al. Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. In DAC, page 173, 2016.Google ScholarGoogle Scholar
  19. [19].Lin C.-C. et al. A 256b-Wordlength ReRAM-based TCAM with Ins search-time and 14x improvement in wordlength-energyefficiency-density product using 2.5T1R cell. In ISSCC, pages 136138, 2016.Google ScholarGoogle Scholar
  20. [20].Ma K. et al. Nonvolatile processor architecture exploration for energy-harvesting applications. IEEE Micro, 35 (5):3240, 2015.Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. [21].Matsunaga S. et al. Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control. In VLSIC, pages 298299, jun 2011.Google ScholarGoogle Scholar
  22. [22].Matsunaga S. et al. A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. In VLSIC, pages 4445, jun 2012.Google ScholarGoogle Scholar
  23. [23].Matsunaga S. et al. Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. In ASP-DAC, pages 475476, jan 2012.Google ScholarGoogle Scholar
  24. [24].Muralimanohar N. et al. CACTI 6.0: A tool to model large caches. HP Lab., pages 2231, 2009.Google ScholarGoogle Scholar
  25. [25].Tsai H.-J. et al. Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI. In DA C, pages 16, june 2015.Google ScholarGoogle Scholar
  26. [26].Dong Xiangyu et al. NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. TCAD, 31 (7):9941007, jul 2012.Google ScholarGoogle Scholar
  27. [27].Xu C. et al. Architecting 3D vertical resistive memory for next-generation storage systems. In ICCAD, pages 5562, nov 2014.Google ScholarGoogle Scholar
  28. [28].Xu C. et al. Modeling and design analysis of 3D vertical resistive memory: A low cost cross-point architecture. In ASP-DA C, pages 825830, jan 2014.Google ScholarGoogle Scholar
  29. [29].Zhao J. et al. Memory and storage system design with nonvolatile memory technologies. IPSJ, 8: 211, 2015.Google ScholarGoogle Scholar
  30. [30].Zuloaga S. et al. Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. In ISCAS, pages 193196, may 2015.Google ScholarGoogle Scholar


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  • Published in

    cover image Guide Proceedings
    2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
    Nov 2016
    946 pages

    Copyright © 2016


    IEEE Press

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    • Published: 7 November 2016


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